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Ordering number : ENN*8075
LC822152
Overview
CMOS IC
CCD-LCD Interface ASIC
LC822152 is a chip which compresses and expands the image inputted from the CCD/CMOS by JPEG format, interfacing the LCD controller equipped with built-in CCD/CMOS sensor module and display memory for DSCPHONEs. Since the I2C master device circuit is embedded in the chip and the signal required for the CCD/CMOS module is supplied from this chip, regarding the CPU, it is not necessary to concern the interface with the CCD/CMOS module. In addition, the zooming function using the H/V scaling circuit allows an effective LCD display. The functions comprises the following blocks : * Image-processing unit where the 8-bit video image data in YUV422 (211) format from CCD/CMOS is scaling processed, performed scaling down and cropping (to cut the four sides) to any size, converted to the RGB565 format and then sent to the LCD controller. * JPEG processing unit where the YUV422 (211) image data (VGA size) input from CCD/CMOS or the image data which has been processed by scaling or cropping is compressed to the JPEG format, and the sign data is output. Or JPEG processing unit where the sign data input from the host is processed with JPEG decryption and sent to the image processing unit. * Thumbnail image processing unit where the image data output to the LCD controller is thinned out and reduced to a maximum 40x40 sized image. * Host control unit where CPU interface, register control, LCD bus switching, JPEG code data transfer, and thumbnail image data transfer are performed. * I2C interface unit for the CCD/CMOS module access. * LCD controller interface processing unit allows the RGB666 output (260,000 colors) supporting the 18-bit parallel and various split transfer.
Features
* CCD/CMOS Interface * CPU Interface * LCD Interface YUV422 (8-bit) format. Maximum VGA size : 640x480. MCKI : System clock supplied to the CCD/CMOS module. PCLK : Dot clock output from the CCD/CMOS module. 80-system 16-bit bus (D15-D0, WR, RD, A2-0, CS) Accessible to the JPEG controller, control register including I2C master, JPEG code buffer, thumbnail image buffer, OSD display buffer, and LCD command buffer. Connects the chip to the LCD controller system bus with the 80-system 16-bit bus interface. It is accessible by switching automatically the two masters, host CPU or LSI imageprocessing unit. Output image from LSI is RGB565 (16-bit) or RGB666 (18-bit, 9-bitx2, etc.). Maximum display size is 320x240 (without OSD) or 320x200 (with OSD). Camera image display to the sub LCD is possible.
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91004 JO IM No.8075-1/11
LC822152
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* I2C Interface * Scaling function * JPEG codec * Thumbnail * Clock system * Package * Process * Power source voltage
Built-in I2C master for CCD/CMOS module control. Without paying attention to the I2C from the CPU, it is accessible to the CCD/CMOS module as well as the normal register (write/read). CCD output is a VGA size (640x480). The output is reduced/cropped to meet the LCD display range with a scaler. Low-pass filter and enhancer are equipped. The YUV422/YUV420 image data is compressed into JPEG code, and the JPEG code data is expanded to the YUV422/YUV420 image data. It performs thinning out, scaling down and cropping the LCD output images to an image size of maximum 40x40. LSI includes PLL and it multiplies the clock input from outside to make a main clock. It divides this multiplied frequency to output to CCD/CMOS module as the clock. FBGA96K 0.18m E/A Internal 1.8V0.18V, I/O 3.0V0.3V
Specifications
Absolute Maximum Ratings at VSS = 0V
Parameter Source Voltage Symbol VDD30 max VDD18 max Input/Output Voltage Input/Output Current Allowable Power Dissipation Operating Temperature Storage Temperature VI, VO I I, IO Pd max Topr Tstg *1 Ta70C *2 Conditions Ratings -0.3 to 3.3 -0.3 to 1.98 -0.3 to *VDD3 max *+0.3 (max 3.3V) 20 650 -30 to +70 -55 to +125 Unit V V V mA mW C C
*1 : Absolute maximum rating per input/output reference cell *2 : This value is assured when the conditions for substrate mounting are as follows. In other conditions, the assured value will be changed accordingly. (Conditions for substrate mounting) Substrate size : FR4 (50mmx108mmx1.27mm) Cu trace rate : 250% Allowable Operating Range at Ta = -30 to +70C, VSS = 0V
Parameter Power Source Voltage (I/O unit) Input Voltage Range (I/O unit) Source Voltage (Internal logic unit) Input Voltage Range (Internal logic unit) Power Source Voltage (Analog part) Input Voltage Range (Analog part) AVIN AVDD VIN18 Symbol VDD30 VIN30 VDD18 Conditions Ratings min 2.7 0 1.62 0 1.62 0 1.8 1.8 typ 3.0 max 3.3 VDD30 1.98 VDD18 1.98 AVDD Unit V V V V V V
Input/Output Pin Capacitance at Ta = 25C, VDD18 = VDD33 = VIN18 = VIN30 = 0V
Parameter Input Pin Output Pin Input/Output Pin Symbol CIN COUT CI/O f = 1MHz f = 1MHz f = 1MHz Conditions Ratings min typ max 10 10 10 Unit pF pF pF
No.8075-2/11
LC822152
Electric Characteristics D.C. Characteristics : Input/Output Levels at Ta = -30 to +70C, VDD30 = 2.7 to 3.3V, VSS = 0V
Parameter Input High Level Voltage Input Low Level Voltage Input High Level Voltage Input Low Level Voltage Input High Level Current Symbol VIH VIL VIH VIL IIH VI = VDD30 VI = VDD30, with pull-down resistor Input Low Level Current Output High Level Voltage IIL VOH VI = VSS IOH = -2mA IOH = -4mA IOH = -8mA Output Low Level Voltage VOL IOL = 1.8mA IOL = 3.6mA IOL = 7.2mA Output Leak Current Pull-down Resistor Non-operating Current Dissipation IOZ RDN IDD Output release VI=VSS or VDD30 At HiZ Output -10 50 100 -10 -10 -10 VDD30-0.8 VDD30-0.8 VDD30-0.8 0.4 0.4 0.4 10 200 300 CMOS support Schmidt 0.75VDD30 0.15VDD30 10 100 10 Conditions CMOS support Ratings min 0.7VDD30 0.2VDD30 typ max Unit V V V V A A A V V V V V V A k A Applicable Pins 2
1 7 6 6, 7 3 8 4 3 8 4 5 6
1 : TEST[3:0], XRST, CLKSEL, STBY, SCANEN, SCANMOD 2 : Input pin and dual-directional pin except 1. 3 : Output pin except MCKI and dual-directional pin except 8. 4 : MCKI 5 : Dual-directional pin 6 : PCLK, HREF, VREF, CD[7:0] 7 : Input pin and dual-directional pin except 6. 8 : D[15:0]
Input Clock
When CLKSEL input is "H".
Clock Pin CKI Maximum Input Frequency (MHz) 60 Duty 5010%
Note : The internal operation clock would be 30MHz at a maximum. For 60MHz input, the clock divided by at least 2 must be used as the internal operation clock. When CLKSEL input is "0" (PLL is used).
Clock Pin CKI Maximum Input Frequency (MHz) 100 Duty 5010%
In addition, setup here must satisfy the following PLL input/output specifications.
Parameter Maximum VCO Oscillation Frequency Minimum VCO Oscillation Frequency Phase Contrast Frequency Symbol f max f min f ref min typ 180 60 30.0 max Unit MHz MHz MHz
No.8075-3/11
LC822152
Package Dimensions
unit : mm 3306
Pin Description
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Pin Number B1 B2 C1 D4 C2 D1 D3 D2 E1 E4 E3 E2 F2 F3 F4 F1 G2 G3 G1 H2 H3 H1 J1 K1 K2 J2 K3 G4 J3 K4 Pin Names VSS AVDD VCNT AVSS TEST3 VDD1.8 VSS VDD3 CKI CLKSEL STBY TEST0 XRST VSS VDD3 CAMPWR REGRES MCKI TEST1 TEST2 SDA SCL VDD1.8 VSS VDD3 PCLK HREF VREF CD7 CD6 I I I I I O O O I I B O I I I I I I O I/O GND Analog system VDD 1.8V power source PLL VCNT pin Analgo VSS Test input 3 1.8V power source GND 3V power source Clock input Clock dividing select Stand by Test input 0 Reset GND 3V power source CCD power down CCD reset CCD master clock Test input 1 Test input 2 I2C data I2C clock 1.8V power source GND 3V power source CCD pixel clock Horizontal synchronous signal input Vertical synchronous signal input CCD data input CCD data input PD PD PD PD PD O O O L L O O L L Pin Description Initial Value
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No.8075-4/11
LC822152
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No. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 Pin Number H4 J4 K5 G5 H5 J5 J6 H6 G6 K6 J7 H7 K7 J8 H8 K8 K9 K10 J10 J9 H10 G7 H9 G10 G8 G9 F10 F7 F8 F9 E9 E8 E7 E10 D9 D8 D10 C9 C8 C10 B10 A10 A9 B9 A8 D7 B8 A7 C7 B7 A6 D6 C6 Pin Names CD5 CD4 CD3 CD2 CD1 CD0 VDD1.8 VSS VDD3 EX1 EX0 LCS2 LA LCS LWR LRD VDD1.8 VSS VDD3 LD15 LD14 LD13 LD12 LD11 LD10 LD9 LD8 LD7 LD6 LD5 VDD3 VSS VDD1.8 LD4 LD3 LD2 LD1 LD0 CS CS2 A1 VSS VDD3 A0 WR RD INT D15 D14 D13 D12 D11 D10 I I I O B B B B B B B B B B B I I I B B B B B B B B B B B B B O O O O O I/O I I I I I I CCD data input CCD data input CCD data input CCD data input CCD data input CCD data input 1.8V power source GND 3V power source Expanded LCD data bus Expanded LCD data bus Chip select output for sub LCD LCD address output LCD chip select output LCD write signal output LCD read signal output 1.8V power source GND 3V power source LCD data bus LCD data bus LCD data bus LCD data bus LCD data bus LCD data bus LCD data bus LCD data bus LCD data bus LCD data bus LCD data bus 3V power source GND 1.8V power source LCD data bus LCD data bus LCD data bus LCD data bus LCD data bus Chip select input Chip select input for sub LCD Address input GND 3V power source Address input Write signal input Read signal input Interrupt output Host data bus Host data bus Host data bus Host data bus Host data bus Host data bus H H 1 H H 1 1 1 1 Pin Description Initial Value PD PD PD PD PD PD
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LC822152
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No. 84 85 86 87 88 89 90 91 92 93 94 95 96 Pin Number B6 B5 C5 D5 A5 B4 C4 A4 B3 C3 A3 A2 A1 Pin Names D9 VDD1.8 VSS D8 D7 D6 D5 D4 D3 D2 D1 D0 VDD3 B B B B B B B B B I/O B Host data bus 1.8V power source GND Host data bus Host data bus Host data bus Host data bus Host data bus Host data bus Host data bus Host data bus Host data bus 3V power source Pin Description Initial Value -
No.8075-6/11
LC822152
Block Diagram
ILC05546
No.8075-7/11
LC822152
AC Characteristics
Host Interface Timing
ILC05547
Symbol tAs tAh tCSh tRDWRs tRDWRh tRwidth tWwidth tDIs tDIh tAcc tDOh ADRESS setup time to CS ADRESS hold time from CS CS hold time from RD/WR
Contents
min 5*1 5*2 0 5*1 5 T+5 20 20 0
max
Unit ns ns ns ns ns ns ns ns ns 50 ns ns
RD/WR(CS)setup time from RD/WR RD/WR(CS)hold time from RD/WR RD pulse width WR pulse width Input DATA setup time to WR Input DATA hold time from WR Output DATA access time from RD Output DATA hold time from RD
2
*1 : Operation at times under 5 ns is also possible by delaying the internal CS with the CS delay setting (CSCHOP register). However, since incorrect operation may occur if an access is performed before the setting is changed, the application must change the setting immediately after power is first applied. *2 : Operation with an internal command access of 0ns minimum is possible. However, if this signal is input at 0ns when the LCD controller is accessed directly, it is possible that small pulses, such as LCS and LCS2, may be generated.
No.8075-8/11
LC822152
ILC05548
Symbol tNACC RD/WR No Access time
Contents JPEG Q-Table Write JPEG Q-Table Read Code/Thumbnail buffer Read Other access
min 3T 7T 4T 2T
Unit ns ns ns ns
Note1 : T is a cycle of ASIC internal clock. (1, 2, 4, or 8 times the cycle of CKI input clock) Note2 : Write access of JPEG Huffman table is subject to the data where access prohibited period is written. CCD Interface Timing
ILC05549
Symbol ts th Setup time to PCLK Hold time from PCLK
Contents
min 10 5
typ
max
Unit ns ns
No.8075-9/11
LC822152
LCD Interface Timing
ILC05550
Symbol tLWRs tLWRwidth tLWRh tLAdly tLDdly tLDh
Contents LCD access setup time to LWR LWR pulse width LCD access hold time from LWR LA delay from cycle start LD delay from cycle start LD hold time from LWR
min T-5 T*n-5 T*m-5
max
Unit ns ns ns 5 10
0 (When m = 0 setup)
tLWRh+5
ns
Note1 : T is a cycle of ASIC internal clock. (1, 2, 4, or 8 times the cycle of CKI input clock) Note2 : n is an ASIC register setting value. Minimum value is 1 (zero). Note3 : m is an ASIC register setting value. Minimum value is 0 (zero). Host-LCD Through Timing
ILC05551
Symbol tLCDdly tLD_h2ldly tLD_l2hdly
Contents HOST to LCD control signal delay HOST to LCD data delay LCD to HOST data delay
min
max 30 35 30
Unit ns ns ns
No.8075-10/11
LC822152
PS No.8075-11/11

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